DS1302 DATASHEET PDF

There are several "real time clock" RTC chips which can be connected to an Arduino. An RTC gives you access to the date and time of day, e. To help keep things simple, we will assume that your RTC module has a battery to keep it "ticking" even when the "main" power to it is not present. This allows us to use our "big" computer to set the date and time in the module "for all time", and not need a way to do the setting in whatever application we are using the RTC for. It has some material which will help users of any microcontroller interface to the RTC, but all of the example code is for Arduino.

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It communicates with a microprocessor via a simple serial interface. The end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. The DS is designed to operate on very low power and retain data and clock information on less than 1 microwatt.

The DS is the successor to the DS In addition to the basic timekeeping functions of the DS, the DS has the additional features of dual power pins for primary and back-up power supplies, programmable trickle charger for VCC1, and seven additional bytes of scratchpad memory. In systems using the trickle charger, the rechargeable energy source is connected to this pin. VCC2 - Vcc2 is the primary power supply pin in a dual supply configuration. V CC1 is connected to a backup source to maintain the time and date in the absence of primary power.

RST Reset - The reset signal must be asserted high during a read or a write. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6 pF. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated.

Each data transfer is initiated by a command byte. The MSB Bit 7 must be a logic 1. If it is 0, writes to the DS will be disabled. Bits 1 through 5 specify the designated registers to be input or output, and the LSB bit 0 specifies a write operation input if logic 0 or read operation output if logic 1.

The command byte is always input starting with the LSB bit 0. The RST input serves two functions. Second, the RST signal provides a method of terminating either single byte or multiple byte data transfer.

A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. Data transfer is illustrated in Figure 3. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written.

This operation permits continuous burst mode read capability. Data is output starting with bit 0. Reads or writes in burst mode start with bit 0 of address 0.

When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not.

When this bit is set to logic 1, the clock oscillator is stopped and the DS is placed into a low-power standby mode with a current drain of less than nanoamps. When this bit is written to logic 0, the clock will start. The initial power on state is not defined. When high, the hour mode is selected. In the hour mode, bit 5 is the second hour bit 20 - 23 hours. The first seven bits bits 0 - 6 are forced to 0 and will always read a 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0.

When high, the write protect bit prevents a write operation to any other register. Therefore the WP bit should be cleared before attempting to write to the device. The simplified schematic of Figure 5 shows the basic components of the trickle charger. The trickle charge select TCS bits bits 4 -7 control the selection of the trickle charger. In order to prevent accidental enabling, only a pattern of will enable the trickle charger. All other patterns will disable the trickle charger. The DS powers up with the trickle charger disabled.

If DS is 01, one diode is selected or if DS is 10, two diodes are selected. The maximum charging current can be calculated as illustrated in the following example. The trickle charger is not accessible in burst mode. At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run.

This eliminates the need to re-read the registers in case of an update of the main registers during a read. In this mode, the 31 RAM registers can be consecutively read or written see Figure 4 starting with bit 0 of address 0. The crystal selected for use should have a specified load capacitance CL of 6 pF. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. A nA mA? All voltages are referenced to ground.

The clock halt flag must be set to logic one oscillator disabled. MM B IN. MM C IN. MM D IN. MM E IN. MM F IN. MM G IN. MM H IN. MM J IN. MM K IN. MM L IN.

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